Polishing processes in semiconductor device manufacturing are generally carried out by chemical mechanical polishing (CMP). Specifically, CMP is used in processes such as shallow trench isolation (STI), planarization of interlayer dielectric films (ILD films), formation of tungsten plugs, and formation of multilayer interconnections composed of copper and a low dielectric film. In STI, one of these processes, it is typical for a silicon oxide layer to be polished and removed by CMP using a silicon nitride layer as a stopper.
As disclosed in Patent Documents 1, 2, and 3, use of cerium oxide abrasive grains is known in specific CMP applications such as STI. Cerium oxide abrasive grains are suitable for use in such applications in that they have an ability to polish and remove silicon oxide more selectively than silicon nitride. Cerium oxide abrasive grains, however, are generally expensive and also disadvantageous in that they easily settle out, thereby being poor in storage stability. Therefore, there has been a need for substituting other abrasive grains such as colloidal silica for cerium oxide abrasive grains. When a polishing composition containing other abrasive grains in place of cerium oxide abrasive grains is used in the same application, the important thing is how to decrease the polishing rate of silicon nitride with the polishing composition without decreasing the polishing rate of silicon oxide.